@zesun33/mcp-yosys mcp_server
Enables AI coding agents and IDEs to synthesize Verilog/SystemVerilog designs with Yosys, inspect cell hierarchies and gate counts, and detect synthesis hazards like inferred latches and combinational loops before physical design flows.
- Link
- https://github.com/zesun33/mcp-yosys
Listing data from Glama (https://glama.ai) — Glama listing
Adoption
- Maintainer
- zesun33
- Repository
- zesun33/mcp-yosys
- GitHub stars
- 0
- Last push
- 2026-10-01
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